PRESENTATION ON: CMOS LATCH UP

CMOS LATCH UP

SLIDE: LATCH UP

Latch Up in CMOS

            Latch Up maybe defined as the creation of a low impedance path between the power supply rails of a CMOS process caused due to the triggering of some innate parasitic device. Obviously, it is a failure mechanism for CMOS integrated circuits, ceasing  its normal functionality either temporarily or permanently.

Primitives of SCR

            Silicon Controlled Rectifier (SCR) is a three terminal power electronic device. It is normally OFF (infact, negligible current flows through it) when it is in FORWARD BLOCKING STATE (upto a turn-on voltage, V_T). In the CONDUCTING STATE, when adequate triggering signal is applied to the GATE terminal its behavior resembles with a forward biased diode (conducts from ANODE to CATHODE) upto a specific voltage value V_K (knee voltage).

            While operating in the conducting state, a considerable amount of current from G is injected into the base of npn transistor. It causes a current flow in the base-emitter junction of the pnp transistor. Consequently the pnp transistor turns on; causing further current to be injected into the base of the npn transistor. The whole setup acts like a positive feedback coupling; where current flowing through each transistor ensures that the other remains in saturation mode. This gives rise to a continual low impedance path between anode and cathode causing erratic current flow through the device beyond V_K. The SCR is said to be in LATCHED STATE.

            Once latched, this arrangement becomes independent of the triggering source (gate terminal). So simply removing it will not turn-off the SCR.

SLIDE: PREVENTION

Parasitic Elements Illustration

            Since all MOS devices are closely located on the die there is the possibility of formation of parasitic SCR devices and with adequate excitation they might conduct as well. As in case of the CMOS inverter illustrated here, the parasitic structure gets triggered when supply voltage exceeds the absolute maximum ratings or improperly managed multiple power supplies are present or input/output pin voltage exceeds either power supply rail by more than a diode drop etc. 

System Approaches

1.	Try to avoid 'hot plug-in' (i.e. make sure power supplies are OFF before plugging a board).
2.	Electro Static Discharge (ESD) at the I/O pads may trigger latch up. Take precautions.
3.	Do not expose the chip to radiation (e.g. X-ray, cosmic ray, α ray). It is capable of penetrating the chip and can contribute excess electron-hole pairs.
4.	Sudden glitches at the power supply rails have to be eliminated preciously.

Design Approaches

1.	Abide by all design rules to avoid formation of parasitic elements.
2.	Substrate should be highly doped to reduce the substrate resistance (RSUB). This will effectively break the path between the collector of pnp-transistor and the base of npn-transistor.
3.	Apply ground to substrate contacts and power-supply to n-well contacts to eliminate sudden voltage glitches that might trigger the parasitic transistors.
4.	Provide guard rings (a doped region surrounding the MOSFET; biased by power-supply for n-type or ground for p-type rings) around p-well and/or n-well to increase the base width of the parasitic transistors and to maintain well-defined potentials (due to biasing).

PREVIEW OF THE PRESENTATION: 
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