4-bit Ripple Carry Counter [Verilog]

The following code is designed using Xilinx ISE 7.1.04i [web-pack] and simulated on ModelSim PE [student edition], both are readily available over Internet for free.
This design has the following features:
1] Negative edge-triggered.
2] Asynchronous active-low reset.
3] 4-bit Type.
[Note: Simulation results and Stimulus (test-bench) is added with the design. It is duly tested for error free functionality.]


Schematics:

 

Verilog Code:
Ripple carry counter:
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
T_FF tff0(q[0], clk, reset);
T_FF tff1(q[1], q[0], reset);
T_FF tff2(q[2], q[1], reset);
T_FF tff3(q[3], q[2], reset);
endmodule 

T flip-flop:
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
D_FF dff0(q, d, clk, reset);
not n1(d, q); // not is Verilog-provided primitive. Case sensitive.
endmodule 

D flip-flop:
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q; 

always @(posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule

Stimulus:
module stimulus_v;
reg clk; // Input
reg reset; // Input
wire [3:0] q; // Output
// Instantiate the Unit Under Test
ripple_carry_counter r1 (.q(q), .clk(clk), .reset(reset));
// Control the clk signal that drives the design block. Cycle time = 10
       initial
              clk = 1'b0; // Set clk to 0
       always
              #5 clk = ~clk; // Toggle clk every 5 time units
// Control the reset signal that drives the design block.
// reset is asserted from 0 to 20 and from 200 to 220 

initial
begin
       reset = 1'b1;
       #20 reset = 1'b0;
       #180 reset = 1'b1;
       #20 reset = 1'b0;
end endmodule

Simulation Data: