Simple Frequency Limiter [VHDL]

The following code is designed using Xilinx ISE 7.1i04 and simulated on Modelsim PE student edition [Both are readily available over Internet for free]

This design acts as a frequency limiter; modifications can be made to this to make it more application specific for advanced implementations. The following code is supported with the test-bench and simulation waveform too for a better understanding. It works in the fashion stated below: There is a system clock (clock_in) which monitors the incoming pulse train (pulse_in). Whenever the frequency of the incoming pulse train goes above the system clock frequency, the system ceases to work (lock goes low). The system automatically retrieves regular functionality by re-asserting the lock, as soon as the foretold condition is met. 

VHDL code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

 
entity frequency_limiter is
port(clock_in, pulse_in : in std_logic;
        lock : out std_logic);
end frequency_limiter;

architecture architecture_ frequency_limiter of frequency_limiter is
signal count : integer := 0;
begin
process(clock_in, pulse_in)
begin
if(rising_edge(clock_in)) then
        count <= 0;
end if;
if(rising_edge(pulse_in)) then
        count <= count + 1;
end if;
end process;
process(count)
begin
if ((count < 1) or (count = 1)) then
        lock <= '1';
else
        lock <= '0';
end if;
end process;
end architecture_lock_status; 

Test Bench: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb_ frequency_limiter IS
END tb_ frequency_limiter;

ARCHITECTURE architecture_ tb_ frequency_limiter OF tb_ frequency_limiter IS
signal lock, clock_in, pulse_in : std_logic := '0';
constant period : time := 20 ps;
BEGIN
uut: entity work.lock_status PORT MAP(clock_in, pulse_in, lock);
clock_in_process :process
                             begin
                             clock_in <= '0';
                             wait for period/2;
                             clock_in <= '1';
                             wait for period/2;
                             end process;
stim_proc: process
                 begin
                 -- case 1:
                 pulse_in <= '1';
                 wait for 5 ps;
                 pulse_in <= '0';
                 wait for 5 ps;
                 -- case 2:
                 pulse_in <= '0';
                 wait for 4 ps;
                 pulse_in <= '1';
                 wait for 4 ps;
                 -- case 3:
                 pulse_in <= '0';
                 wait for 5 ps;
                 pulse_in <= '1';
                 wait for 4 ps;
                 -- case 4:
                 pulse_in <= '0';
                 wait for 4 ps;
                 pulse_in <= '1';
                 wait for 5 ps;
                 -- case 5:
                 pulse_in <= '0';
                 wait for 4 ps;
                 pulse_in <= '1';
                 wait;
                 end process;
END architecture_ tb_ frequency_limiter; 

Simulation Data: